Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
As is known, n-type or n-channel transistors, such as NMOS transistors, may be put in a saturated or conductive state responsive to application of a positive logic level voltage to a gate layer (“gate”) thereof. Such n-type transistors may be put in a non-conductive state responsive to application of a negative logic level voltage, such as ground for example, to the gate. However, even with a grounded gate, n-type devices may have what is known as subthreshold voltage leakage. This leakage allows for what is known as a leakage current. Even though leakage current for an individual n-type transistor may be relatively small, the cumulative effect of leakage current for many n-type transistors may be significant. This cumulative leakage current may therefore have a significant impact on standby current, and accordingly contribute to power consumption of an FPGA. For FPGAs, there may be many circuit resources that are unused in an application, and accordingly the standby current associated with only unused circuit resources may be significant.
As n-type transistors of FPGAs become smaller, conventionally threshold voltage levels likewise become smaller. With a reduction in transistor threshold voltage levels, subthreshold voltage leakage may increase. This increase in subthreshold voltage leakage may be exponential, and accordingly the standby current associated with circuit resources of an FPGA, whether used or not used in an instantiated design, may be significantly increased with smaller threshold voltages.
As is known, a body bias voltage (“Vbb”), which may also be called back body bias voltage, reverse body bias voltage, back gate bias voltage, or back gate voltage, may be applied to a body of an n-type transistor to reduce subthreshold leakage. For use with n-type transistors, Vbb is conventionally applied as a negative voltage to a p-type transistor body. As most integrated circuits do not have an external pin for receiving an externally provided negative voltage, such integrated circuits conventionally include a negative voltage generator. However, a negative voltage generator consumes power. Thus, a target Vbb is conventionally selected such that there is a net positive reduction in consumed power; in other words, power saved by reduction in standby current is at least greater than power consumed by the negative voltage generator and associated circuitry used to provide Vbb. Use of the negative voltage generator is conventionally regulated for efficient application of Vbb. For example, if Vbb becomes too negative for an application, reliability of body-biased n-type transistors may be adversely affected.
Accordingly, it would be desirable and useful to provide means to enhance regulated provisioning of Vbb to facilitate reducing standby current while efficiently operating a negative voltage generator. Moreover, it would be desirable and useful to provide means to enhance regulated provisioning of Vpp to facilitate reducing standby current while efficiently operating a positive voltage generator for p-type transistors. Furthermore, as PLDs conventionally have not employed negative voltage generators to produce Vbb, it would be additionally desirable and useful if such means were applicable to PLDs, including FPGAs.